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| d a t a sh eet preliminary speci?cation file under integrated circuits 2000 sep 07 integrated circuits SC2000 universal timeslot interchange
2000 sep 07 2 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 package mechanical drawing . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 scbus/st-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 peb mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 cpu data switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 internal bus data switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 logical pin organization . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 physical pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 microprocessor interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 command/status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 internal register memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 version/revision register (o4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 destination routing memory (80h-9fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 source routing memory (a0h-bfh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 destination parallel access registers (c0h-dfh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 source parallel access registers (e0h-ffh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 crecommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 timing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 microprocessor interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 local and expansion bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 clock and sync input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2000 sep 07 3 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 features multi-time slot switching capability for n x 64k channels (n = 1 to 32). architecture optimized for the call processing environment: scsa tm , peb tm , or mvip tm compatible. two software selectable expansion bus formats: scbus tm /st-bus tm peb two software selectable local bus formats: st-bus peb enhanced input hysteresis threshold. 32 x 2048 channel switch serial or parallel access to the scbus. internal support for scbus clock fallback built-in scbus message bus interface supports both intel?and motorola? processor interfaces 68-pin plcc package 5v cmos technology 0.995 [25.27] 0.985 [25.02] 0.800 [20.32] ref 0.995 [25.27] 0.985 [25.02] 0.800 [20.32] ref 0.048 [1.22] 0.042 [1.07] pin 1 index 0.130 [3.30] 0.090 [2.29] 0.056 [1.42] 0.042 [1.07] 0.200 [5.08] 0.165 [4.19] clkfail& mc bus configuration registers parallel access registers routing memory switch matrix timing local bus interface micro- processor interface expansion bus interface mc rx data mc tx data microprocessor bus si so clock in clock out clkfail mc expansion serial bus expansion clock out block diagram package mechanical drawing 2000 sep 07 4 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 overview the SC2000 is a custom vlsi circuit optimized for use in the call processing environment. the SC2000 provides a cost-effective means of implementing the interface between a high speed internal tdm bus and an external (expansion) tdm bus. internal buffer- ing allows the exchange of data between tdm buses of different speeds and architectures. the SC2000 supports two external bus formats; scbus/st-bus and peb, and two internal bus formats; scbus/ st-bus and peb. it is compatible with scsa, peb, or mvip requirements. scbus operation is also compatible with the siemens pcm highway. the switching function and operational configurations of the SC2000 are fully software programmable. the processor bus interface is pin configured, allowing ease of use with a wide variety of indus- try-standard cpus. description the primary function of the SC2000 is to exchange digital data between the time slot on the local bus and the time slot on the expansion bus . a micropro- cessor interface allows the host cpu to define the time slots and serial streams between which the data is exchanged. scbus/st-bus mode in scbus mode the serial streams of the external bus can be programmed to operate at 2.048 mbps, 4.096 mbps or 8.192 mbps. the local bus will always operate at 2.048 mbps. the local-to-external bus switch con- nection is defined by the contents of the destination routing memory. there are 32 destination routing memory loca- tions, one corresponding to each time slot of the local bus. the data stored in the destination routing memory selects the time slot and serial stream of the ex- pansion bus to which the local bus input (si) will be connected. the external-to-local bus switch con- nection is defined by the contents of the source routing memory. there are 32 source routing memory locations, one corresponding to each time slot of the local bus. the data stored in the source routing memory selects the time slot and serial stream to which the local bus out- put (so) will be connected. writing data into the routing memories is synchronized with the scbus timing so that routing data is only changed on frame boundaries. all serial data is buffered in holding reg- isters. the entire contents of the holding register are transferred to the output registers on frame boundaries. this architecture introduces a constant one-frame delay through the switch. this constant delay allows bundled time slots to be switched. peb mode in peb mode the serial streams of the external bus and the local bus may be selected to run at either 1.544 mbps or 2.048 mbps. when peb mode is selected, one of four peb configurations may be used: 1. peb resource mode, without switching. 2. peb network mode, without switching. 3. peb resource mode, with switching. 4. peb network mode, with switching. when switching is not selected the serial data is simply buffered between the local bus and the peb. this maintains the data position relative to the multi-frame sync and allows robbed-bit or cas signals to propagate transparently. when switching is selected the serial data is transferred between the local and peb buses via the switching matrix. the one-frame delay that occurs requires that robbed-bit or cas signals be handled specially. the advantages of modes with switching are: timing delays between the local and peb bus are decoupled by the switch matrix the local bus can access all peb data lines (serr, sert, and l_sert) so can be set to high impedance on frame boundaries, allowing a bi-directional local bus to be implemented non-switching modes are the only con- figurations that support an interface to an asynchronous peb. cpu data switching in addition to switching local bus serial data to and from the external bus, the SC2000 also allows the cpu to write data directly to the external bus. the chip provides a frame-sync generated interrupt which enables a group of time slots to be accessed from the same frame. internal bus data switching the source routing memory local connect enable selects the switching of data from any si time slot to any so time slot. this operation introduces a constant two-frame delay, as the data passes through the switch twice. loopback mode the scbus loopback mode electrically isolates the SC2000 from the external bus but still allows access to the local bus. this mode is intended for isolating the board from the external bus while diagnostic tests are being run. a clk_in source is required for this mode. the recommended clk_in frequencies are 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz, or 32.768 mhz. 2000 sep 07 5 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 additional features the so output may be set to high im- pedance on frame boundaries by setting the source routing memory switch output enable bit. this allows outputs from multiple devices to be connected to a common line. the so signal may also be configured as an open collector output. the data sample position of both local and external buses is selectable between 50% and 75% of the bit width. logical and physical pinout diagrams SC2000 d_7 d_6 d_5 d_4 d_3 d_2 d_1 d_0 a_1 a_0 cs* rd*(strb*) wr*(r/w*) reset i*(m) plcc68 int (clkt) sclkx2* (fsynct) sclk (msynct) rsrvd (sert) fsync* (sigt) clkfail (l_clkt) sd_0 (l_fsynct) sd_1 (l_msynct) sd_2 (l_tsx*) sd_3 (l_sert) sd_4 (l_sigt) sd_5 (clkr) sd_6 (fsyncr) sd_7 (msyncr) sd_8 (serr) sd_9 (sigr) sd_10 (r_clkt) sd_11 (r_fsynct) sd_12 (r_msynct) sd_13 (r_tsx*) sd_14 (r_sert) sd_15 (r_sigt) mc so_clk si_clk so_fs si_fs so_ms si_ms so rxd 35 55 57 58 59 61 62 63 65 66 67 1 3 4 5 7 8 9 11 12 13 15 16 41 40 48 47 46 44 43 53 24 26 27 29 30 31 32 33 37 38 23 22 20 18 17 50 52 39 54 clk_in sync_in si txd 1 2 3 4 5 6 7 8 9 61 62 63 64 65 66 67 68 35 34 33 32 31 30 29 28 27 43 42 41 40 39 38 37 36 int d_0 d_1 d_2 d_3 d_4 d_5 s0 s0_clk s1_clk s1 a_0 a_1 sd_5 sd_6 sd_7 sd_8 sd_9 sd_10 sd_11 clkfail sd_1 sd_0 sd_2 sd_3 sd_4 18 17 16 15 14 13 12 11 10 26 25 24 23 22 21 20 19 52 53 54 55 56 57 58 59 60 44 45 46 47 48 49 50 51 sync_in rxd txd sclkx2* sclk rsrvd fsync* si_ms so_ms si_fs so_fs clk_in reset i* mc sd_15 sd_14 sd_13 sd_12 d_6 d_7 cs* rd* wr* SC2000 68-pin plcc (top view) physical pinout logical pin organization 2000 sep 07 6 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 pin description pin name input/output pin number pin description d_0 - d_7 i/o 33, 32, 31, 30, 29, 27, 26, 24 data bus. these bi-directional, tri-state lines are the SC2000s interface to the cpu data bus. a_0, a_1 i 38, 37 address bus. these inputs select the internal register used by a read or write operation. normally connected to cpu address lines a0 and a1 in 8-bit cpu systems, or a1 and a2 in 16-bit cpu systems. cs* i 23 chip select. this active low input selects the chip for a read or write operation. i* i 17 bus interface mode select. this input selects intel- and motorola-type data bus interface configurations. 0 = intel. 1 = motorola. rd* or strb* i i 22 i* = 0. read this active low input enables the data bus drivers to drive the cpu data bus with the contents of the internal register selecte d by a_0 and a_1. i* = 1. strobe during a read operation a low on this input enables the data bus drivers to drive the cpu data bus with the contents of the int ernal register selected by a_0 and a_1. during a write operation data is transferred from the cpu data bus to the register selected b y a_0 and a_1 on a low to high transition of this signal. wr* or r/w* i i 20 i* = 0. write during a write operation data is transferred from the cpu data bus to the register selected by a_0 and a_1 on a low to high transition of this signal. i* = 1. read/write this input selects between a write operation (r/w* = 0) and a read operation (r/w* =1). reset i 18 reset. this active high input forces all outputs to tri-state, and resets the SC2000 chip. clk_in i 50 local clock input. sync_in i 52 local sync input. si i 39 serial input. local serial bus data input line. so o 43 serial output. local serial bus data output line. txd i 54 transmit data scbus message bus transmit data input line. int o 35 interrupt request. active high interrupt request output line. sclkx2* or clkt i/o i 55 register bit c_4 = 0. scbus system clock x 2. register bit c_4 = 1. peb transmit clock. sclk or fsynct i/o i 57 register bit c_4 = 0. scbus system clock. register bit c_4 = 1. peb frame sync. rsrvd or msynct i i 58 register bit c_4 = 0. scbus reserved. register bit c_4 = 1. peb transmit multi-frame sync. fsync* or sert i/o i 59 register bit c_4 = 0. scbus frame sync. register bit c_4 = 1. peb transmit serial data. clkfail i/o 61 register bit c_4 = 0. scbus clock fail signal. sd_0 or l_clkt i/o i/o 62 register bit c_4 = 0. scbus serial data stream 0. register bit c_4 = 1. peb local resource transmit clock. sd_1 or l_fsynct i/o i/o 63 register bit c_4 = 0. scbus serial data stream 1. register bit c_4 = 1. peb local resource transmit frame sync. sd_2 or l_msynct i/o i/o 65 register bit c_4 = 0. scbus serial data stream 2. register bit c_4 = 1. peb local resource multi-frame sync. sd_3 or l_tsx* i/o i/o 66 register bit c_4 = 0. scbus serial data stream 3. register bit c_4 = 1. peb local resource transmit time slot enable. 2000 sep 07 7 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 sd_4 or l_sert i/o i/o 67 register bit c_4 = 0. scbus serial data stream 4. register bit c_4 = 1. peb local resource transmit serial data. sd_5 i/o 1 register bit c_4 = 0. scbus serial data stream 5. sd_6 or clkr i/o i/o 3 register bit c_4 = 0. scbus serial data stream 6. register bit c_4 = 1. peb receive clock. sd_7 or fsyncr i/o i/o 4 register bit c_4 = 0. scbus serial data stream 7. register bit c_4 = 1. peb receive frame sync. sd_8 or msyncr i/o i/o 5 register bit c_4 = 0. scbus serial data stream 8. register bit c_4 = 1. peb receive multi-frame sync. sd_9 or serr i/o i/o 7 register bit c_4 = 0. scbus serial data stream 9. register bit c_4 = 1. peb receive data stream. sd_10 i/o 8 register bit c_4 = 0. scbus serial data stream 10. sd_11 i/o 9 register bit c_4 = 0. scbus serial data stream 11. sd_12 i/o 11 register bit c_4 = 0. scbus serial data stream 12. sd_13 i/o 12 register bit c_4 = 0. scbus serial data stream 13. sd_14 i/o 13 register bit c_4 = 0. scbus serial data stream 14. sd_15 i/o 15 register bit c_4 = 0. scbus serial data stream 15. mc i/o 16 register bit c_4 = 0. scbus message bus signal. so_clk o 41 serial output clock. clock for local serial output data. si_clk o 40 serial input clock. clock for local serial input data. so_fs o 48 serial output frame sync. frame sync for local serial output data. si_fs o 47 serial input frame sync. frame sync for local serial input data. so_ms o 46 serial output multi-frame sync. multi-frame sync for local serial output data. si_ms o 44 serial input multi-frame sync. multi-frame sync for local serial input data. rxd o 53 receive data. message channel serial data output. vddo1 - vddo5 power 2, 10, 25, 45, 60 i/o pad v dd (+5 v). vddi1 - vddi3 power 19, 34, 51 core v dd (+5 v). vsso1 - vsso7 power 6, 14, 28, 42, 56, 64, 68 i/o pad vss (gnd). vssi1 - vssi3 power 21, 36, 49 core vss (gnd). pin name input/output pin number pin description pin description (continued) 2000 sep 07 8 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 register description microprocessor interface registers the four 8-bit microprocessor interface registers comprise the command and control port for the SC2000. command/status register busy (cs_0): this bit is automatically set to 1 when a command that requires synchronization with the SC2000? in- ternal state machine has been initiated. the bit is cleared to 0 when the com- mand has been completed. the follow- ing commands require synchronization: destination routing memory write source routing memory write parallel access destination write parallel access source read read (cs_1): setting this bit to 1 ini- tiates a read of the register pointed to by the contents of the internal address register. once the busy bit is read as cleared to 0 the contents of the selected register will be available in the low byte and high byte data registers. once the read operation is complete the read bit is cleared automatically. write (cs_2): setting this bit to 1 ini- tiates a write to the register pointed to by the contents of the internal address register. once the busy bit has been cleared to 0 the contents of the low byte and high byte data registers have been transferred into the selected register. once the write operation is com- pleted the write bit is cleared auto- matically. terminate (cs_3): setting this bit to 1 terminates any command that requires synchronization with the SC2000? in- ternal state machine. this command is needed to complete a command when the SC2000? internal state machine has stopped running due to the failure of the system clocks. the command currently being executed is completed asynchro- nously and the busy bit is cleared to 0. to restore normal operation the ter- minate bit must be explicitly cleared to 0. this bit can be read back for verifi- cation purposes. command/status register bit r/w command/status 0 r cs_0: busy (s) 1 w cs_1: read (c) 2 w cs_2: write (c) 3 r/w cs_3: terminates (c) 4 cs_4: reserved 5 cs_5: reserved 6 cs_6: reserved 7 r/w cs_7: reset (c) note: (1) bit 0 is the lsb of the byte. (2) initiating multiple commands in a single access is not recommended. cpu interface register map a_1 a_0 register name 0 0 command/status 0 1 internal address 1 0 low byte data 1 1 high byte data low byte data register bit r/w function 0 r/w d_0 1 r/w d_1 2 r/w d_2 3 r/w d_3 4 r/w d_4 5 r/w d_5 6 r/w d_6 7 r/w d_7 note: bit 0 is the lsb of the byte. high byte data register bit r/w function 0 r/w d_8 1 r/w d_9 2 r/w d_10 3 r/w d_11 4 r/w d_12 5 r/w d_13 6 r/w d_14 7 r/w d_15 note: bit 0 is the lsb of the byte. 2000 sep 07 9 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 reset (cs_7): setting this bit to 1 forces the SC2000 into its reset state, and initializes all internal registers. this command reproduces the function of the reset pin. setting this bit to 0 returns the SC2000 to normal operation. this bit can be read back for verification purposes. internal registers the internal registers are accessed by reads and writes to the data registers using the address held in the internal address register. internal register memory map values for a_7 .. a_0 (h) function r/w 00 . . 03 configuration 1 . . configuration 4 r/w 04 version/revision r/w 05 . . 7f reserved . . reserved r/w 80 . . 9f destn routing . . destn routing r/w a0 . . bf source routing . . source routing r/w c0 . . df destn parallel . . destn parallel r/w e0 . . ff source parallel . . source parallel r/w configuration registers configuration register 1(00h) global output enable (c_0): clearing this bit to 0 forces all outputs to the high impedance state, with the exception of the microprocessor interface data bus. setting this bit to 1 enables all outputs. this bit is cleared on reset. expansion bus timing driver enable (c_1): when scbus mode is selected (c_4 = 0), clearing this bit to 0 disables the expansion bus timing drivers. when peb resource mode is selected (c_6, c_4 = 01), this bit has no effect. when peb network mode is selected (c_6, c_4 = 11), clearing this bit to 0 disables the expansion bus drivers clkr, l_clkt, fsyncr, l_fsynct, msyncr, and l_msynct. setting this bit to 1 enables these timing drivers. this bit is cleared on reset. framing mode (c_3, c_2): this two-bit field selects the number of bits per frame (b/f), time slots per frame (ts/f) and frames per multi-frame (f/mf) on both the local and expansion bus. when scbus mode is selected (c_4 = 0), there is no multi-frame sync signal available on the expansion bus. the (00) combination of (c_3, c_2) is invalid. in this case the internal multi-frame sync will be free running, and synchronous to fsync. when peb mode is selected (c_4 = 1) the only valid combinations of (c_3, c_2) are (00) and (01). these bits are cleared on reset. expansion bus interface select (c_4): this bit selects the expansion bus inter- face operating mode. clearing this bit to 0 selects scbus mode. setting this bit to 1 selects peb mode. this bit is cleared on reset. configuration register 1 bit function 0 c_0: global output enable 1 c_1: expansion bus timing driver enable 2 3 c_2: framing mode 0 c_3:framing mode 1 4 c_4: expansion bus interface select 5 c_5: scbus loopback mode 6 7 c_6: peb module type 0 c_7:peb module type 1 note: bit 0 is the lsb of the low byte data register. expansion bus c_3, c_2 b/f ts/f f/mf 00 193 24 12 01 256 32 16 10 512 64 16 11 1024 128 16 local bus c_3, c_2 b/f ts/f f/mf 00 193 24 12 01 256 32 16 10 256 32 16 11 256 32 16 2000 sep 07 10 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 scbus loopback mode select (c_5): when scbus mode is selected (c_4 = 0), this bit controls the scbus loopback. clearing this bit to 0 disables loopback mode. setting this bit to 1 enables loop- back mode. when peb mode is selected (c_4 = 1) this bit has no effect. when loopback is enabled the expan- sion bus timing and data bus drivers are forced to high impedance, and the data outputs are looped back internally to the corresponding inputs. this mode is used to test the SC2000 without disrupting the operation of the scbus. a clock must be supplied at clk_in for operation in loopback mode. this bit is cleared on reset. peb module type (c_7, c_6): when peb mode is selected (c_4 = 1) this two-bit field selects the peb module type. when scbus mode is selected (c_4 = 0) these bits have no effect. these bits are cleared on reset. configuration register 2 (01h) peb module type c_7, c_6 operating mode 00 resource module without switching 01 network module without switching 10 resource module with switching 11 network module with switching configuration register 2 bit function 0 1 2 c_8: clk_in divider 0 c_9: clk_in divider 1 c_10: clk_in divider 2 3 c_11: sync_in format 4 5 c_12: sync_in select 0 c_13: sync_in select 1 6 7 c_14: peb network modul timing select 0 c_15: peb network modul timing select 1 note: bit 0 is the lsb of the low byte data register. clk_in divider (c_10, c_9, c_8): this field selects the clk_in division ratio used in the generation of the sys- tem source clock. when ?lk_in divide by 1?and scbus mode are selected and the expansion bus timing drivers are enabled (c_10, c_9, c_8, c_4, c_1 = 00001), then sclkx2* is held high and the fsync* period is equal to 1 sclk period. these bits are cleared on reset. sync_in format (c_11): this bit selects the sync_in format to be either peb conventional or st-bus. if this bit is cleared to 0 then sync_in is taken to be in the peb conventional format. if this bit is set to 1, sync_in is taken to be in the st-bus format. in st-bus format the clk_in signal is inverted to produce the system clock source. this bit is cleared on reset. sync_in select (c_13, c_12): this two bit field selects the function of the sync_in input. these bits are cleared on reset. peb network module timing select (c_15, c_14): when peb network module mode is selected (c_6, c_4, c_1 = 111), this two bit field selects the module timing mode. otherwise these bits have no effect. these bits are cleared on reset. configuration register 3 (02h) clk_in divider c_10, c_9, c_8 clk_in divided by 000 1 001 2 010 4 011 8 100 16 101 reserved 110 reserved 111 reserved sync_in select c_13, c_12 sync_in function 00 ignored 01 frame sync 10 ignored 11 multi-frame sync peb network module timing mode c_15, c_14 timing mode 00 master 01 master, msynct ? l_msynct 10 slave, msynct ? msyncr 11 slave, sync_in ? msyncr configuration register 3 bit function 0 c_16: expansion bus data sample position 1 c_17: local bus data sample position 2 c_18: scbus output driver 3 c_19: so output driver 4 c_20: local bus framing format 5 c_21: message channel txd select 6 7 c_22: sert mux 0 c_23: sert mux 1 note: bit 0 is the lsb of the low byte data register. 2000 sep 07 11 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 expansion bus data sample position (c_16): when scbus mode is selected (c_4 = 0) this bit determines the location of the sampled point in the bit cell. when this bit is cleared to 0, sampling occurs at 50% of the bit width. when this bit is set to 1, sampling occurs at 75% of the bit width. when peb mode is selected (c_4 = 1) this bit has no effect, and data is always sampled at the 50% point. sclkx2* must be present in order to sample at the 75% point. this bit is cleared on reset. local bus data sample position (c_17): when scbus mode is selected (c_4 = 0) this bit determines the loca- tion of the sample point in the bit cell. when this bit is cleared to 0 sampling occurs at 50% of the bit width. when this bit is set to 1, sampling occurs at 75% of the bit width. when peb mode is selected (c_4 = 1) this bit has no effect, and data is always sampled at the 50% point. sclkx2* must be present in order to sample at the 75% point. this bit is cleared on reset. scbus output driver (c_18): when scbus mode is selected (c_4 = 0), this bit determines the scbus output driver type. when this bit is cleared to 0, the output drivers are configured as tri-state type. when this bit is set to 1 the output drivers are configured as open collector type. when peb mode is selected (c_4 = 1) this bit has no effect. peb outputs are always driven open collector. all scbus outputs are affected by this bit with the exception of clkfail and mc, which are always driven open collector. this bit is cleared on reset. so output driver (c_19): this bit determines the so output driver type. when this bit is cleared to 0 the output drivers are configured as tri-state. when this bit is set to 1 the output drivers are configured as open collector. when peb mode without switching is selected (c_7, c_4 = 01) then so is always enabled. this bit is cleared on reset. local bus framing format (c_20): when scbus mode is selected (c_4 = 0) this bit determines the local bus framing format. when this bit is cleared to 0 the local bus operates with peb conventional framing format. when this bit is set to 1 the local bus op- erates with st-bus framing format. when peb mode is selected (c_4 = 1) this bit has no effect. with st-bus framing format selected, si_clk is replaced by c4*, si_fs by f0*, and si_ms by m0*. so_clk, so_fs and so_ms are unaffected by the status of this bit, and continue to output peb conventional framing. sclkx2* must be present, or sclk must be at least twice the local clock (clk_in) frequency for st-bus fram- ing format to be used. this bit is cleared on reset. message channel txd select (c_21): when scbus mode is selected (c_4 = 0) this bit determines the configuration of the txd input. when this bit is cleared to 0, the txd input is configured as a transparent buffer. when this bit is set to 1 the txd input is configured as a latched buffer. when peb mode is selected (c_4 = 1), this bit has no effect. mc is not used in peb mode. when a transparent buffer is selected (c_21 = 0), the hdlc controller should output txd on the rising edge of so_clk. when a latched buffer is selected (c_21 = 1) the hdlc control- ler should output txd on the falling edge of so_clk. this bit is cleared on reset. sert mux (c_23, c_22): when peb network mode is selected, this two bit field selects the source of data for the lo- cal bus so serial stream. when scbus mode (c_7, c_6, c_4 = xx0) or peb resource mode (c_7, c_6, c_4 = 001) are selected, these bits have no effect. configuration register 4 (03h) clkfail latch (c_24): when scbus mode is selected (c_4 = 0) this bit indi- cates the status of the clkfail latch. 0 ? clkfail clear 1 ? clkfail set when peb mode is selected (c_4 = 1), this bit is always clear. st-bus framing format replacements peb conventional st-bus si_clk c4* si_fs f0* si_ms m0* peb data source stream c_23, c_22 data source 00 l_sert 01 (l_sert* !l_tsx*) +(sert* l_tsx*) configuration register 4 bit function 0 c_24: clkfail latch 1 c_25: cfsync latch 2 c_26: clkfail latch clear* 3 c_27: fsync latch clear* 4 c_28: clkfail polarity 5 c_29: int mask* 6 c_30: int polarity 7 c_31: int ouput driver note: bit 0 is the lsb of the low byte data register. 2000 sep 07 12 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 fsync latch (c_25): when scbus mode (c_4 = 0) or peb mode with switching (c_7, c_4 = 11) are selected, these bits indicate the status of the fsync latch. 0 ? fsync clear 1 ? fsync set when a peb mode without switching is selected (c_7, c_4 = 01) this bit is always clear. clkfail latch clear* (c_26): this bit resets the clkfail latch. clearing this bit to 0 clears the clkfail latch and disables clkfail interrupts. setting this bit to 1 enables clkfail interrupts. this bit is cleared on reset. fsync latch clear* (c_27): this bit resets the fsync latch. clearing this bit to 0 clears the fsync latch and disables fsync interrupts. setting this bit to 1 enables fsync interrupts. this bit is cleared on reset. clkfail polarity (c_28): this bit controls the level of the clkfail signal which will set the clkfail latch. when this bit is cleared to 0, the clkfail latch is set when the clkfail signal is ?o?(0). when this bit is set to 1 the clkfail latch is set when the clkfail signal is ?i?(1). the ?lkfail = 0?interrupt mode is used by the new clock master to deter- mine that clock fall back has been exe- cuted effectively. the ?lkfail = 1? interrupt mode is used by the standby clock board to detect clock failure. this bit should only be changed when the clkfail interrupt is disabled (c_26 = 0). this bit is cleared on reset. int mask* (c_29): this bit controls the interrupts generated by clkfail and fsync (int = clkfail + fsync). when this bit is cleared to 0 all inter- rupts are masked. when this bit is set to 1, interrupts are enabled. the status of this bit does not affect the clkfail latch or fsync latch bits (c_24 and c_25), and these bits can still be used to determine the status of the two latches. this bit is cleared on reset. int output polarity (c_30): this bit controls the active level of the int inter- rupt output. when this bit is cleared to 0, then the int output is active low. when this bit is set to 1 then the int output is active high. this bit is cleared on reset. int output driver (c_31): this bit controls the configuration of the int output driver. when this bit is cleared to 0, the int output driver is configured as open collector. when this bit is set to 1 the int output driver is configured as totem-pole. version/revision register (04h): the version/revision register is an 8-bit read-only register used to identify the version and revision status of a particu- lar batch of SC2000s. it is recommended that a test of this field be included in all firmware interface code to ensure com- patibility. the initial release of the SC2000 will be version/revision = 00h. destination routing memory (80h - 9fh): the destination routing memory maps time slots from the local si bus onto the expansion bus. each location in the destination routing memory corresponds to a time slot on the local si bus. the contents of each location specify a time slot on the expansion bus. the contents of all destination routing memory locations are cleared on re- set. when writing data into the destination routing memory the low byte data register contains a 7-bit binary field holding a time slot number, and the high data byte register contains a 4-bit binary field holding a port (stream) number. together these two fields uniquely identify a time slot on the expansion bus which will be the destin- ation for data from the local si bus. version/revision register 1 bit function 0 rev 0 1 rev 1 2 rev 2 3 rev 3 4 ver 0 5 ver 1 6 ver 2 7 ver 3 note: bit 0 is the lsb of the low byte data register. destination routing memory map iar destination map 80h channel 0 81h channel 1 82h channel 2 . . . . 9fh channel 31 note: iar = internal address register contents. channel n is equivalent to time slot n on the local si bus. 2000 sep 07 13 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 time slot select (dr_6 .. dr_0): this 7-bit field specifies a time slot number between 0 and 127. dr_6 is the msb of this field. port select (dr_11 .. dr_8): when scbus mode is selected (c_4 = 0) this 4-bit field specifies an scbus data stream number between 0 and 15. dr_11 is the msb of this field. when a peb mode with switching is selected (c_6, c_4 = 11) this 4- bit field specifies a peb data stream. see table for details. destination routing memory lsb bit function 0 1 2 3 4 5 6 dr_0: time slot select 0 dr_1: time slot select 1 dr_2: time slot select 2 dr_3: time slot select 3 dr_4: time slot select 4 dr_5: time slot select 5 dr_6: time slot select 6 7 dr_7: reserved note: bit 0 is the lsb of the low byte data register. destination routing memory msb bit function 0 1 2 3 dr_8: port select 0 dr_9: port select 1 dr_10: port select 2 dr_11: port select 3 4 dr_12: reserved 5 dr_13: reserved 6 dr_14: parallel access enable 7 dr_15: switch output enable note: bit 0 is the lsb of the high byte data register. parallel access enable (dr_14): when this bit is cleared to 0, the SC2000 uses the local si bus as the source of data for the expansion bus. when this bit is set to 1 the SC2000 uses the contents of the corresponding destination parallel access register as the source of expan- sion bus data. switch output enable (dr_15): when this bit is cleared to 0, the SC2000 ex- pansion bus drivers are forced to the high impedance state during the speci- fied time slot period. when this bit is set to 1 the SC2000 expansion bus drivers drive the bus during the specified time slot period. source routing memory (a0h - bfh): the source routing memory maps time slots from the expansion bus onto time slots on the local so bus. each location in the source routing memory corresponds to a time slot on the local so bus. destination port select (peb mode) dr_11..dr_8 peb destination 0h l_sert/l_tsx* 1h serr 2h r_sert/r_tsx* 3h sert 4h . . fh reserved . . reserved source routing memory iar source mapping a0h channel 0 a1h channel 1 a2h channel 2 . . . . bfh channel 31 note: iar = internal address register contents. channel n is equivalent to time slot n on the local s0 bus. the contents of all source routing memory location are cleared on reset. when writing data into the source routing memory the low byte data register contains a 7-bit binary field holding a time slot number, and the high data byte register contains a 4-bit binary field holding a port (stream) number. together these two fields uniquely identify a time slot on the expansion bus which will be used as a source of data for a time slot on the local so bus. time slot select (sr_6 .. sr_0): this 7-bit field specifies a time slot number between 0 and 127. sr_6 is the msb of this field. port select (sr_11 .. sr_8): when scbus mode is selected (c_4 = 0), this 4-bit field specifies an scbus data stream number between 0 and 15. sr_11 is the msb of this field. when a peb mode with switching is selected (c_6, c_4 = 11) this 4-bit field specifies a peb data stream as follows: source routing memory lsb bit function 0 1 2 3 4 5 6 sr_0: time slot select 0 sr_1: time slot select 1 sr_2: time slot select 2 sr_3: time slot select 3 sr_4: time slot select 4 sr_5: time slot select 5 sr_6: time slot select 6 7 sr_7: reserved note: bit 0 is the lsb of the low byte data register. 2000 sep 07 14 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 sr_11 is the msb of this field. local connect enable (sr_14): this bit controls the internal connection time slots on the local bus. when this bit is cleared to 0 local connect is disabled. when this bit is set to 1 local connect is enabled and a time slot on the local si bus will be connected internally to a time slot on the local so bus. when local connect is enabled the source routing memory time slot select bits (sr_0 .. sr_6) select the destination time slot on the local so bus. the contents of the port select field (sr_8 .. sr_11) are ignored. switch output enable (sr_15): when this bit is cleared to 0 the local so bus drivers are forced to the high impedance state during the specified time slot pe- riod. when this bit is set to 1 the local so bus drivers drive the bus during the specified time slot period. destination parallel access registers (c0h .. dfh): if parallel access and switch output are enabled, the device cpu can write data to the expansion bus via these SC2000 registers. the write mapping is controlled by the destina- tion routing memory. the contents of the selected parallel access register will replace the contents of the local si bus time slot that would otherwise have been transferred to the expansion bus. source parallel access registers ( e0h .. ffh): the source parallel access registers are continually loaded with the data being written to the corre- sponding local so bus time slot, irre- spective of the status of the parallel access enable or switch output enable bits. if local connect is enabled this data will originate from the local si bus. source routing memory msb bit function 0 1 2 3 sr_8: port select 0 sr_9: port select 1 sr_10: port select 2 sr_11: port select 3 4 sr_12: reserved 5 sr_13: reserved 6 sr_14: local connect enable 7 sr_15: switch output enable note: bit 0 is the lsb of the high byte data register. peb mode source data stream sr_11..sr_8 source peb stream 0h sert mux 1h serr 2h r_sert 3h sert 4h . . fh reserved . . reserved destination parallel access regs iar si destination c0h channel 0 c1h channel 1 c2h channel 2 . . . . dfh channel 31 note: iar = internal address register con- tents. channel n is equivalent to time slot n on the local si bus. source parallel access regs iar so destination e0h channel 0 e1h channel 1 e2h channel 2 . . . . ffh channel 31 note: iar = internal address register con- tents. channel n is equivalent to time slot n on the local so bus. 2000 sep 07 15 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 electrical characteristics absolute maximum ratings recommended dc operating conditions dc electrical characteristics symbol parameter test conditions minimum maximum unit t s storage temperature -65 150 c v i input voltage -0.5 7 v p d package power dissipation 1 w note: 1. voltages are with respect to ground (v ss ) unless otherwise stated. symbol parameter test conditions minimum maximum unit t a ambient temperature 0 70 c v dd supply voltage 4.75 5.25 v note: 1. voltages are with respect to ground (v ss ) unless otherwise stated. symbol parameter test conditions minimum maximum unit i dd supply (voltage) current 100 ma v ih input high voltage 2.0 v dd +0.5 v v il input low voltage -0.5 1.0 v vh ys input hysteresis voltage 0.4 v i li input leakage current v i = v dd or v ss 10 m a c i input capacitance 7 pf v oh1 output high voltage (1) i oh = -24 ma 2.4 v v ol1 output low voltage (1) i ol = 24 ma 0.4 v v oh2 output high voltage (2) i oh = -4 ma 2.4 v v ol2 output low voltage (2) i ol = 4 ma 0.4 v i lo output leakage current v o = v dd or v ss 10 m a c io output or i/o capacitance 7 pf notes: 1. v oh1 , v ol1 apply to expansion bus interface (scbus/peb) signals. 2. v oh2 , v ol2 apply to all other signals. 3. voltages are with respect to ground (v ss ) unless otherwise stated. 4. input hysteresis voltage: indicates that when the input is interpreted as high (2.0 volts), it will be interpreted "high" un til the input is dropped below 1.6 volts. likewise, a low input will be interpreted as "low" until the input goes above 1.4 volts. 2000 sep 07 16 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 figure 1. microprocessor interface timing ?intel bus mode table 1. microprocessor interface timing ?intel bus mode symbol parameter min typ max unit t1 cs* setup to wr* - 30 ns t2 cs* hold from wr* - 20 ns t3 rd* setup to cs* 10 ns t4 rd* hold from cs* 10 ns t5 wr* pulse width 30 ns t6 wr* hold from cs* 10 ns t7 a_[1:0] setup to wr* - 30 ns t8 a_[1:0] hold from wr* - 20 ns t9 d_[7:0] setup to wr* - 30 ns t10 d_[7:0] hold from wr* - 20 ns t11 rd* hold from cs* 10 ns t12 wr* setup to cs* 10 ns t13 wr* hold from cs* 10 ns t14 d_[7:0] valid delay from cs* 40 ns t15 d_[7:0] valid delay from rd* 40 ns t16 d_[7:0] valid delay from a_[1:0] 40 ns t17 d_[7:0] float delay from cs* 25 ns t18 d_[7:0] float delay from rd* 25 ns note: 1. timing measured with 100 pf load on d_[7:0]. t1 t2 t3 t4 t11 t5 t6 t12 t13 t7 t8 t9 t10 t14 t15 t16 t17 t18 cs* rd* wr* a_[1:0] d_[7:0] 2000 sep 07 17 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 figure 2. microprocessor interface timing ?motorola bus mode table 2. microprocessor interface timing ?motorola bus mode symbol parameter min typ max unit t1 cs* setup to strb* - 30 ns t2 cs* hold from strb* - 20 ns t3 strb* pulse width 30 ns t4 strb* hold from cs* 10 ns t5 r/w* setup to strb* 10 ns t6 r/w* hold from strb* 10 ns t7 a_[1:0] setup to strb* - 30 ns t8 a_[1:0] hold from strb* - 20 ns t9 d_[7:0] setup to strb* - 30 ns t10 d_[7:0] hold from strb* - t11 strb* hold from cs* 10 ns t12 r/w*setup to strb* 10 ns t13 r/w*hold from strb* 10 ns t14 d_[7:0] valid delay from cs* 40 ns t15 d_[7:0] valid delay from strb* 40 ns t16 d_[7:0] valid delay from a_[1:0] 40 ns t17 d_[7:0] float delay from cs * 25 ns t18 d_[7:0] float delay from strb* 25 ns note: 1. timing measured with 100 pf load on d_[7:0]. t1 t2 t3 t4 t11 t5 t6 t12 t13 t7 t8 t9 t10 t14 t15 t16 t17 t18 cs* strb* r/w* a_[1:0] d_[7:0] 20 ns 2000 sep 07 18 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 sclkx2* sclk fsync* si_clk so_clk si_fs,si_ms so_fs,so_ms so si sd_[15:0] output sd_[15:0] input txd mc rxd 2000 sep 07 19 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 table 3. local bus interface timing ?scbus mode (2.048 mbps) symbol parameter min typ max unit t1 sclkx2* low time 122 ns t2 sclkx2* high time 122 ns t3 sclkx2* period 244 ns t4 sclk low time 244 ns t5 sclk high time 244 ns t6 sclk period 488 ns t7 fsync* setup to sclk - 0 n s t8 fsync* hold from sclk - 15 ns t9 si_clk delay from sclkx2* 40 ns t10 si_clk - delay from sclkx2* - 40 ns t11 so_clk - delay from sclk - 40 ns t12 so_clk delay from sclk 40 ns t13 si_fs, si_ms delay from sclkx2* - 45 ns t14 si_fs, si_ms - delay from sclkx2* - 45 ns t15 so_fs, so_ms - delay from sclk - 45 ns t16 so_fs, so_ms delay from sclk - 45 ns t17 so float to valid delay from sclk - 40 ns t18 so valid to valid delay from sclk - 40 ns t19 so valid to float delay from sclk - 25 ns t20 si setup to sclk (50% sample position) 0 ns t21 si hold from sclk (50% sample position) 25 ns t22 si setup to sclkx2* - (75% sample position) 0 ns t23 si hold from sclkx2* - (75% sample position) 25 ns t24 sd_[15:0] float to valid delay from sclk - 35 ns t25 sd_[15:0] valid to valid delay from sclk - 35 ns t26 sd_[15:0] valid to float delay from sclk - 25 ns t27 sd_[15:0] setup to sclk (50% sample) 0 ns t28 sd_[15:0] hold from sclk (50% sample) 25 ns t29 sd_[15:0] setup to sclkx2* - (75% sample) 0 ns t30 sd_[15:0] hold from sclkx2* - (75% sample) 25 ns t31 txd setup to sclk - (registered mc) 0 ns t32 txd hold from sclk - (registered mc) 25 ns t33 mc delay from sclk - (registered mc) 85 ns t34 mc delay from txd (passed through mc 80 ns t35 rxd delay from mc 35 ns notes: 1. timing measured with 100 pf load on all local bus outputs, 200 pf load on all scbus outputs. 2. mc timing measured with 200 pf, 470 w pullup (4.7 k w /10). open collector low to high transitions include 61 ns delay from hi-z to 2.4 v. 3. si_clk, si_fs and si_ms shown in st-bus framing format. when in peb conventional framing format si_clk, si_fs and si_ms have identical timing to so_clk, so_fs and so_ms. 4. so shown configured as tri-state driver. 5. so_ms, si_ms are free-running multi-frame synchronization signals that occur once every 16 frames. 2000 sep 07 20 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 figure 4. local bus interface timing ?scbus mode (4.096 mbps) t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 sclkx2* sclk fsync* si_clk so_clk si_fs,si_ms so_fs,so_ms so si sd_[15:0] output sd_[15:0] input txd mc rxd 2000 sep 07 21 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 table 4. local bus interface timing ?scbus mode (4.096 mbps) symbol parameter min typ max unit t1 sclkx2* low time 61 ns t2 sclkx2* high time 61 ns t3 sclkx2* period 122 ns t4 sclk low time 122 ns t5 sclk high time 122 ns t6 sclk period 244 ns t7 fsync* setup to sclk - 0ns t8 fsync* hold from sclk - 15 ns t9 si_clk delay from sclk - 40 ns t10 si_clk - delay from sclk 40 ns t11 so_clk - delay from sclk - 40 ns t12 so_clk delay from sclk - 40 ns t13 si_fs, si_ms delay from sclk 45 ns t14 si_fs, si_ms - delay from sclk 45 ns t15 so_fs, so_ms - delay from sclk - 45 ns t16 so_fs, so_ms delay from sclk - 45 ns t17 so float to valid delay from sclk - 40 ns t18 so valid to valid delay from sclk - 40 ns t19 so valid to float delay from sclk - 25 ns t20 si setup to sclk - (50% sample position) 0 ns t21 si hold from sclk - (50% sample position) 25 ns t22 si setup to sclk (75% sample position) 0 ns t23 si hold from sclk (75% sample position) 25 ns t24 sd_[15:0] float to valid delay from sclk - 35 ns t25 sd_[15:0] valid to valid delay from sclk - 35 ns t26 sd_[15:0] valid to float delay from sclk - 25 ns t27 sd_[15:0] setup to sclk (50% sample) 0 ns t28 sd_[15:0] hold from sclk (50% sample) 25 ns t29 sd_[15:0] setup to sclkx2* - (75% sample) 0 ns t30 sd_[15:0] hold from sclkx2* - (75% sample) 25 ns t31 txd setup to sclk - (registered mc) 0 ns t32 txd hold from sclk - (registered mc) 25 ns t33 mc delay from sclk - (registered mc) 85 ns t34 mc delay from txd (passed through mc) 80 ns t35 rxd delay from mc 35 ns notes: 1. timing measured with 100 pf load on all local bus outputs, 200 pf load on all scbus outputs. 2. mc timing measured with 200 pf, 470 w pullup (4.7 k w /10). open collector low to high transitions include 61 ns delay from hi-z to 2.4 v. 3. si_clk, si_fs and si_ms shown in st-bus framing format. when in peb conventional framing format si_clk, si_fs and si_ms have identical timing to so_clk, so_fs and so_ms. 4. so shown configured as tri-state driver. 5. so_ms, si_ms are free-running multi-frame synchronization signals that occur once every 16 frames. 2000 sep 07 22 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 figure 5. local bus interface timing ?scbus mode (8.192 mbps) t1 t3 t2 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 sclkx2* sclk fsync* si_clk so_clk si_fs,si_ms so_fs,so_ms so si sd_[15:0] output sd_[15:0] input txd mc rxd 2000 sep 07 23 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 table 5. local bus interface timing ?scbus mode (8.192 mbps) symbol parameter min typ max unit t1 sclkx2* low time 30.5 ns t2 sclkx2* high time 30.5 ns t3 sclkx2* period 61 ns t4 sclk low time 61 ns t5 sclk high time 61 ns t6 sclk period 122 ns t7 fsync* setup to sclk - 0 ns t8 fsync* hold from sclk - 15 ns t9 si_clk delay from sclk - 40 ns t10 si_clk - delay from sclk - 40 ns t11 so_clk - delay from sclk - 40 ns t12 so_clk delay from sclk - 40 ns t13 si_fs, si_ms delay from sclk - 45 ns t14 si_fs, si_ms - delay from sclk - 45 ns t15 so_fs, so_ms - delay from sclk - 45 ns t16 so_fs, so_ms delay from sclk - 45 ns t17 so float to valid delay from sclk - 40 ns t18 so valid to valid delay from sclk - 40 ns t19 so valid to float delay from sclk - 25 ns t20 si setup to sclk - (50% sample position) 0 ns t21 si hold from sclk - (50% sample position) 25 ns t22 si setup to sclk - (75% sample position) 0 ns t23 si hold from sclk - (75% sample position) 25 ns t24 sd_[15:0] float to valid delay from sclk - 35 ns t25 sd_[15:0] valid to valid delay from sclk - 35 ns t26 sd_[15:0] valid to float delay from sclk - 25 ns t27 sd_[15:0] setup to sclk (50% sample) 0 ns t28 sd_[15:0] hold from sclk (50% sample) 25 ns t29 sd_[15:0] setup to sclkx2* - (75% sample) 0 ns t30 sd_[15:0] hold from sclkx2* - (75% sample) 25 ns t31 txd setup to sclk - (registered mc) 0 ns t32 txd hold from sclk - (registered mc) 25 ns t33 mc delay from sclk - (registered mc) 85 ns t34 mc delay from txd (passed through mc) 80 ns t35 rxd delay from mc 35 ns notes: 1. timing measured with 100 pf load on all local bus outputs, 200 pf load on all scbus outputs. 2. mc timing measured with 200 pf, 470 w pullup (4.7 k w /10). open collector low to high transitions include 61 ns delay from hi-z to 2.4 v. 3. si_clk, si_fs and si_ms shown in st-bus framing format. when in peb conventional framing format si_clk, si_fs and si_ms have identical timing to so_clk, so_fs and so_ms. 4. so shown configured as tri-state driver. 5. so_ms, si_ms are free-running multi-frame synchronization signals that occur once every 16 frames. 2000 sep 07 24 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 figure 6. local bus interface timing ?peb resource module without switching t1 t2 t3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 clkr so_clk fsyncr so_fs msyncr so_ms serr so l_clkt si_clk l_fsynct si_fs l_msynct si_ms si l_sert l_tsx* 2000 sep 07 25 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 table 6. local bus interface timing ?peb resource module without switching symbol parameter min typ max unit t1a clkr, l_clkt high time (1.544 mbps) 323 ns t1b clkr, l_clkt high time (2.048 mbps) 244 ns t2a clkr, l_clkt low time (1.544 mbps) 323 ns t2b clkr, l_clkt low time (2.048 mbps) 244 ns t3a clkr, l_clkt period (1.544 mbps) 647 ns t3b clkr, l_clkt period (2.048 mbps) 488 ns t4 so_clk - delay from clkr - 35 ns t5 so_clk delay from clkr 35 ns t6 so_fs - delay from fsyncr - 35 ns t7 so_fs delay from fsyncr 35 ns t8 so_ms - delay from msyncr - 35 ns t9 so_ms delay from msyncr 35 ns t10 so delay from serr 35 ns t11 si_clk - delay from l_clkt - 35 ns t12 si_clk delay from l_clkt 35 ns t13 l_fsynct setup to l_clkt 5 ns t14 l_fsynct hold from l_clkt 15 ns t15 si_fs - delay from l_fsynct - 35 ns t16 si_fs delay from l_fsynct 35 ns t17 si_ms - delay from l_msynct - 35 ns t18 si_ms delay from l_msynct 35 ns t19 l_sert enable delay from l_clkt - 70 ns t20 l_sert delay from si 60 ns t21 l_sert disable delay from l_clkt - 70 ns t22 l_tsx* delay from l_clkt - 35 ns t23 l_tsx* - delay from l_clkt - 70 ns notes: 1. timing measured with 100 pf load on all local bus outputs, 200 pf 220/330 w termination on all peb outputs. open collector low to high transitions include 43 ns delay from hi-z to 2.4 v. 2. l_tsx* occurs on time slot boundaries. 2000 sep 07 26 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 figure 7. local bus interface timing ?peb network module without switching t1 t2 t3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 l_clkt so_clk l_fsynct so_fs l_msynct so_ms sert, l_sert l_tsx* so clkr si_clk fsyncr si_fs msyncr si_ms si serr 2000 sep 07 27 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 table 7. local bus interface timing ?peb network module without swithing symbol parameter min typ max unit t1a l_clkt, clkr high time (1.544 mbps) 323 ns t1b l_clkt, clkr high time (2.048 mbps) 244 ns t2a l_clkt, clkr low time (1.544 mbps) 323 ns t2b l_clkt, clkr low time (2.048 mbps) 244 ns t3a l_clkt, clkr period (1.544 mbps) 647 ns t3b l_clkt, clkr period (2.048 mbps) 488 ns t4 so_clk - delay from l_clkt - 35 ns t5 so_clk delay from l_clkt 35 ns t6 so_fs - delay from l_fsynct - 35 ns t7 so_fs delay from l_fsynct 35 ns t8 so_ms - delay from l_msynct - 35 ns t9 so_ms delay from l_msynct 35 ns t10 so delay from sert, l_sert 35 ns t11 so delay from l_tsx* 35 ns t12 si_clk - delay from lclkr - 35 ns t13 si_clk delay from l_clkr 35 ns t14 fsyncr setup to clkr 5 ns t15 fsyncr hold from clkr 15 ns t16 si_fs - delay from fsyncr - 35 ns t17 si_fs delay from fsyncr 35 ns t18 si_ms - delay from msyncr - 35 ns t19 si_ms delay from msyncr 35 ns t20 serr enable delay from clkr - 70 ns t21 serr delay from si 60 ns t22 serr disable delay from clkr - 70 ns note: 1. timing measured with 100 pf load on all local bus outputs, 200 pf 220/330 w termination on all peb outputs. open collector low to high transitions include 43 ns delay from hi-z to 2.4 v. 2000 sep 07 28 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 figure 8. local bus interface timing ?peb resource module with switching t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 clkr so_clk, si_clk fsyncr so_fs, si_fs msyncr so_ms l_msynct si_ms so si ser output ser input tsx* output tsx* input 2000 sep 07 29 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 table 8. local bus interface timing ?peb resource module with switching symbol parameter min typ max unit t1a clkr high time (1.544 mbps) 323 ns t1b clkr high time (2.048 mbps) 244 ns t2a clkr low time (1.544 mbps) 323 ns t2b clkr low time (2.048 mbps) 244 ns t3a clkr period (1.544 mbps) 647 ns t3b clkr period (2.048 mbps) 488 ns t4 so_clk, si_clk - delay from clkr - 35 ns t5 so_clk, si_clk delay from clkr 35 ns t6 fsyncr setup to clkr 5 ns t7 fsyncr hold from clkr 15 ns t8 so_fs, si_fs - delay from fsyncr - 35 ns t9 so_fs, si_fs delay from fsyncr 35 ns t10 so_ms - delay from msyncr - 35 ns t11 so_ms delay from msyncr 35 ns t12 si_ms - delay from l_msynct - 35 ns t13 si_ms delay from l_msynct 35 ns t14 so float to valid delay from clkr - 40 ns t15 so valid to valid delay from clkr - 40 ns t16 so valid to float delay from clkr - 25 ns t17 si setup to clkr 0 ns t18 si hold from clkr 25 ns t19 ser enable delay from clkr - 70 ns t20 ser valid delay from clkr - 70 ns t21 ser disable delay from clkr - 70 ns t22 ser setup to clkr 0 ns t23 ser hold from clkr 25 ns t24 tsx* delay from clkr - 35 ns t25 tsx* - delay from clkr - 70 ns t26 tsx* setup to clkr 0 ns t27 tsx* hold from clkr 25 ns notes: 1. timing measured with 100 pf load on all local bus outputs, 200 pf 220/330 w termination on all peb outputs. open collector low to high transitions include 43 ns delay from hi-z to 2.4 v. 2. ser = l_sert, serr, r_sert, sert. 3. tsx* = l_tsx*, r_tsx*. 2000 sep 07 30 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 figure 9. local bus interface timing ?peb network module with switching t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 clkr so_clk, si_clk fsyncr so_fs, si_fs l_msynct so_ms msyncr si_ms so si ser output ser input tsx* output tsx* input 2000 sep 07 31 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 table 9. local bus interface timing ?peb network module with switching symbol parameter min typ max unit t1a clkr high time (1.544 mbps) 323 ns t1b clkr high time (2.048 mbps) 244 ns t2a clkr low time (1.544 mbps) 323 ns t2b clkr low time (2.048 mbps) 244 ns t3a clkr period (1.544 mbps) 647 ns t3b clkr period (2.048 mbps) 488 ns t4 so_clk, si_clk - delay from clkr - 35 ns t5 so_clk, si_clk delay from clkr 35 ns t6 fsyncr setup to clkr 5 ns t7 fsyncr hold from clkr 15 ns t8 so_fs, si_fs - delay from fsyncr - 35 ns t9 so_fs, si_fs delay from fsyncr 35 ns t10 so_ms - delay from l_msynct - 35 ns t11 so_ms delay from l_msynct 35 ns t12 si_ms - delay from msyncr - 35 ns t13 si_ms delay from msyncr 35 ns t14 so float to valid delay from clkr - 40 ns t15 so valid to valid delay from clkr - 40 ns t16 so valid to float delay from clkr - 25 ns t17 si setup to clkr 0 ns t18 si hold from clkr 25 ns t19 ser enable delay from clkr - 70 ns t20 ser valid delay from clkr - 70 ns t21 ser disable delay from clkr - 70 ns t22 ser setup to clkr 0 ns t23 ser hold from clkr 25 ns t24 tsx* delay from clkr - 35 ns t25 tsx* - delay from clkr - 70 ns t26 tsx* setup to clkr 0 ns t27 tsx* hold from clkr 25 ns notes: 1. timing measured with 100 pf load on all local bus outputs, 200 pf 220/330 w termination on all peb outputs. open collector low to high transitions include 43 ns delay from hi-z to 2.4 v. 2. ser = l_sert, serr, r_sert, sert. 3. tsx* = l_tsx*, r_tsx*. 2000 sep 07 32 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 figure 10. clk_in, sync_in ?scbus mode (clk_in divider 3 4) table 10. clk_in, sync_in ?scbus mode (clk_in divider 3 4) symbol parameter min typ max unit t1 clk_in period 122 ns t2 clk_in high time 61 ns t3 clk_in low time 61 ns t4 sync_in low setup to clk_in (peb conventional) 10 ns t5 sync_in low hold from clk_in (peb conventional) 10 ns t6 sync_in high setup to clk_in (peb conventional) 10 ns t7 sync_in high hold from clk_in (peb conventional) 10 ns t8 sync_in setup to clk_in (st-bus) 10 ns t9 sync_in hold from clk_in (st-bus) 10 ns t10a sclkx2* delay from clk_in - (peb conventional) 25 ns t10b sclkx2* delay from clk_in (st-bus) 25 ns t11a sclkx2* - delay from clk_in - (peb conventional) 25 ns t11b sclkx2* - delay from clk_in (st-bus) 25 ns t12a sclk - delay from clk_in - (peb conventional) 25 ns t12b sclk - delay from clk_in (st-bus) 25 ns t13a sclk delay from clk_in - (peb conventional) 25 ns t13b sclk delay from clk_in (st-bus) 25 ns t14 fsync* delay from sclkx2* - 30 ns t15 fsync* - delay from sclkx2* - 30 ns note: 1. timing measured with 200 pf load on all scbus outputs. t1 t2 t3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10a t10b t11a t11b t12a t12b t13a t13b t14 t15 clk_in (conventional) sync_in (conventional) clk_in (st-bus) sync_in (st-bus) sclkx2* sclk fsync* 2000 sep 07 33 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 figure 11. clk_in, sync_in ?scbus mode (clk_in divider = 2) table 11. clk_in, sync_in ?scbus mode (clk_in divider = 2) symbol parameter min typ max unit t1 clk_in period 244 ns t2 clk_in high time 122 ns t3 clk_in low time 122 ns t4 sync_in low setup to clk_in (peb conventional) 10 ns t5 sync_in low hold from clk_in (peb conventional) 10 ns t6 sync_in high setup to clk_in (peb conventional) 10 ns t7 sync_in high hold from clk_in (peb conventional) 10 ns t8 sync_in setup to clk_in (st-bus) 10 ns t9 sync_in hold from clk_in (st-bus) 10 ns t10a sclkx2* delay from clk_in - (peb conventional) 25 ns t10b sclkx2* delay from clk_in (st-bus) 25 ns t11a sclkx2* - delay from clk_in (peb conventional) 25 ns t11b sclkx2* - delay from clk_in - (st-bus) 25 ns t12a sclk - delay from clk_in - (peb conventional) 25 ns t12b sclk - delay from clk_in (st-bus) 25 ns t13a sclk delay from clk_in - (peb conventional) 25 ns t13b sclk delay from clk_in (st-bus) 25 ns t14 fsync* delay from sclkx2* - 30 ns t15 fsync* - delay from sclkx2* - 30 ns note: 1. timing measured with 200 pf load on all scbus outputs. t1 t2 t3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10a t10b t11a t11b t12a t12b t13a t13b t14 t15 clk_in (conventional) sync_in (conventional) clk_in (st-bus) sync_in (st-bus) sclkx2* sclk fsync* 2000 sep 07 34 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 figure 12. clk_in, sync_in ?scbus mode (clk_in divider = 1) table 12. clk_in, sync_in ?scbus mode (clk_in divider = 1) symbol parameter min typ max unit t1 clk_in period 488 ns t2 clk_in high time 244 ns t3 clk_in low time 244 ns t4 sync_in low setup to clk_in (peb conventional) 10 ns t5 sync_in low hold from clk_in (peb conventional) 10 ns t6 sync_in high setup to clk_in (peb conventional) 10 ns t7 sync_in high hold from clk_in (peb conventional) 10 ns t8 sync_in setup to clk_in (st-bus) 10 ns t9 sync_in hold from clk_in (st-bus) 10 ns t10a sclk - delay from clk_in - (peb conventional) 25 ns t10b sclk - delay from clk_in (st-bus) 25 ns t11a sclk delay from clk_in (peb conventional) 25 ns t11b sclk delay from clk_in - (st-bus) 25 ns t12 fsync* delay from sclk 30 ns t13 fsync* - delay from sclk 30 ns note: 1. timing measured with 200 pf load on all scbus outputs. t1 t2 t3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10a t10b t11a t11b t12 t13 clk_in (conventional) sync_in (conventional) clk_in (st-bus) sync_in (st-bus) sclkx2* sclk fsync* 2000 sep 07 35 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 figure 13. clk_in, sync_in ?peb network master mode (clk_in divider 3 2) t1 t2 t3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10a t10b t11a t11b t12 t13 t14 t15 t16 t18 t17 t19 clk_in (conventional) sync_in (conventional) clk_in (st-bus) sync_in (st-bus) clkr, l_clkt fsyncr, l_fsynct msynct msyncr l_msynct 2000 sep 07 36 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 table 13. clk_in, sync_in ?peb network master mode (clk_in divider 3 2) symbol parameter min typ max unit t1 clk_in period 244 ns t2 clk_in high time 122 ns t3 clk_in low time 122 ns t4 sync_in low setup to clk_in (peb conventional) 10 ns t5 sync_in low hold from clk_in (peb conventional) 10 ns t6 sync_in high setup to clk_in (peb conventional) 10 ns t7 sync_in high hold from clk_in (peb conventional) 10 ns t8 sync_in setup to clk_in (st-bus) 10 ns t9 sync_in hold from clk_in (st-bus) 10 ns t10a clkr, l_clkt - delay from clk_in - (peb conventional) 60 ns t10b clkr, l_clkt - delay from clk_in (st-bus) 60 ns t11a clkr, l_clkt delay from clk_in - (peb conventional) 30 ns t11b clkr, l_clkt delay from clk_in (st-bus) 30 ns t12 fsyncr, l_fsynct - delay from clkr - 70 ns t13 fsyncr, l_fsynct delay from clkr - 35 ns t14 msyncr - delay from clkr - 70 ns t15 msyncr delay from clkr - 35 ns t16 l_msynct - delay from clkr - 70 ns t17 l_msynct delay from clkr - 35 ns t18 l_msynct - delay from msynct - 60 ns t19 l_msynct delay from msynct 25 ns note: 1. timing measured with 200 pf 220/330 w termination on all peb outputs. open collector low to high transitions include 43 ns delay from hi-z to 2.4 v. 2000 sep 07 37 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 figure 14. clk_in, sync_in ?peb network master mode (clk_in divider = 1) t1 t2 t3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10a t10b t11a t11b t12 t13 t14 t15 t16 t18 t17 t19 clk_in (conventional) sync_in (conventional) clk_in (st-bus) sync_in (st-bus) clkr, l_clkt fsyncr, l_fsynct msynct msyncr l_msynct 2000 sep 07 38 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 table 14. clk_in, sync_in ?peb network master mode (clk_in divider = 1) symbol parameter min typ max unit t1 clk_in period 488 ns t2 clk_in high time 244 ns t3 clk_in low time 244 ns t4 sync_in low setup to clk_in (peb conventional) 10 ns t5 sync_in low hold from clk_in (peb conventional) 10 ns t6 sync_in high setup to clk_in (peb conventional) 10 ns t7 sync_in high hold from clk_in (peb conventional) 10 ns t8 sync_in setup to clk_in (st-bus) 10 ns t9 sync_in hold from clk_in (st-bus) 10 ns t10a clkr, l_clkt - delay from clk_in - (peb conventional) 60 ns t10b clkr, l_clkt - delay from clk_in (st-bus) 60 ns t11a clkr, l_clkt delay from clk_in (peb conventional) 30 ns t11b clkr, l_clkt delay from clk_in - (st-bus) 30 ns t12 fsyncr, l_fsynct - delay from clkr - 70 ns t13 fsyncr, l_fsynct delay from clkr - 35 ns t14 msyncr - delay from clkr - 70 ns t15 msyncr delay from clkr - 35 ns t16 l_msynct - delay from clkr - 70 ns t17 l_msynct delay from clkr - 35 ns t18 l_msynct - delay from msynct - 60 ns t19 l_msynct delay from msynct 25 ns note: 1. timing measured with 200 pf 220/330 w termination on all peb outputs. open collector low to high transitions include 43 ns delay from hi-z to 2.4 v. 2000 sep 07 39 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 figure 15. peb network slave table 15: peb network slave symbol parameter min typ max unit t1 clkt period 488 ns t2 clkt high time 244 ns t3 clkt low time 244 ns t4 clkr, l_clkt - delay from clkt - 60 ns t5 clkr, l_clkt delay from clkt 25 ns t6 sync_in low setup to clkr 0 ns t7 sync_in low hold from clkr 20 ns t8 sync_in high setup to clkr 0 ns t9 sync_in high hold from clkr 20 ns t10 fsyncr, l_fsynct - delay from fsynct - 60 ns t11 fsyncr, l_fsynct delay from fsynct 25 ns t12 msyncr - delay from msynct - 60 ns t13 msyncr delay from msynct 25 ns t14 msyncr - delay from clkr - 70 ns t15 msyncr delay from clkr - 35 ns t16 l_msynct - delay from msynct - 60 ns t17 l_msynct delay from msynct 25 ns note: 1. timing measured with 200 pf 220/330 w termination on all peb outputs. open collector low to high transitions include 43 ns delay from hi-z to 2.4 v. t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t14 t13 t15 t16 t17 clkt clkr, l_clkt sync_in fsynct fsyncr, l_fsynct msynct msyncr l_msynct 2000 sep 07 40 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 2000 sep 07 41 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable 2000 sep 07 42 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 data sheet status note 1. please consult the most recently issued data sheet before initiating or completing a design. data sheet status product status definitions (1) objective speci?cation development this data sheet contains the design target or goal speci?cations for product development. speci?cation may change in any manner without notice. preliminary speci?cation quali?cation this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. product speci?cation production this data sheet contains ?nal speci?cations. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2000 sep 07 43 philips semiconductors preliminary speci?cation universal timeslot interchange SC2000 notes ? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 70 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, marketing communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 5f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2451, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 60/14 moo 11, bangna trad road km. 3, bagna, bangkok 10260, tel. +66 2 361 7910, fax. +66 2 398 3447 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 02/pp 44 date of release: 2000 sep 07 document order number: 9397 750 07433 |
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